The present invention relates generally to semiconductor fabrication methods and systems. The present invention also relates to semiconductor fuses and methods for fabricating such semiconductor fuses.
Some types of integrated circuitry utilize fuses. A fuse is a structure, which can be broken down or blown in accordance with a suitable electrical current, which is provided through the fuse to provide an open circuit condition. Within the context of integrated circuitry memory devices, fuses can be used to program in redundant rows of memory. Fuses have use in other integrated circuitry applications as well. Semiconductor fusible links are used for both activating redundancy in memory chips and for programming functions and codes in logic chips. Typical fusible links are large structures blown by heat, e.g. from a laser, or from electrical current passed through the fuse.
Many integrated circuits such as dynamic random access memory (DRAM) and static random access memory (SRAM) employ fuses. Such fuses can provide for redundancy for the purpose of preventing reduction of yield of the semiconductor devices, which may be caused by random defects generated in the manufacturing process. The redundant circuit portion is provided as a spare circuit portion having the same function as a specific circuit portion so that the specific circuit portion, which has a defect caused during manufacturing may be replaced with the redundant circuit in order to maintain the function of the entire semiconductor. Moreover, fuse links provide for voltage options, packaging pin out options, or any other option desired by the manufacturer to be employed prior to the final processing. This helps increase yield and makes it easier to use one basic design for several different end products.
In the fabrication of integrated circuit (IC) structures, fusible links (i.e., fuses) thus play an important role in improving the yield of the fabrication process. In general, as indicated above, it is desirable to provide redundancy in certain elements of the circuitry of an electronic component and the faulty element could be removed via a fuse and the component still be used. Two types of such fuses are in use. In one type, the fuse element is blown using an external heat source, e.g., laser beam. In a second type, flowing an electrical current through the fuse element generally blows the fuse. Electrical fuses are preferred as the fuse blow operation could be automated with a circuit test.
Three paramount requirements for a fuse are: a) material and process compatibility with thin film processes used to make the component; b) be capable of a clean blow meaning that a minimal amount of residue is left after the blow; and c) voltage compatibility with the circuitry used if an electrical blow is used.
The rapid increase of hand held IC devices has opened up a new world of low voltage circuitry for weight and power conservation. These type IC devices require a fuse, which could be blown clean at or below 2.5 V. The low power circuitry also requires very high conductivity interconnection lines in the device. To meet this requirement, copper metallurgy is the preferred choice; which, in turn, mandates use of a Damascene process to make the device. Aluminum may also be employed to form the interconnection lines using known procedures.
In general, multilayer electronic components comprise multiple layers of a dielectric material having metallization on each layer in the form of vias, pads, straps connecting pads to vias and wiring. Vias or other openings in the dielectric layer extend from one layer to another layer. These openings are filled with a conductive material and electrically connect the metallization on one layer to the metallization on another layer and provide for the high density electronic components devices now used in industry.
An important aspect of multilayer electronic components is the via or openings between layers in which a conductive material is applied to provide electrical contact between the metallization on different layers. Broadly stated, the typical multilayer electronic component is built up from a number of layers of a dielectric material layer such as silicon oxide, fluorinated silicon oxide, polymers including polyimide and fluorinated polyimide, ceramics, carbon and other dielectric materials. In the processing sequence known in the art as the xe2x80x9cDamascene Processxe2x80x9d, the dielectric layer is patterned using known techniques such as the use of a photoresist material, which is exposed to define the wiring pattern. After developing, the photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. This is generally termed a lithography or photolithography process or operation and may be used for both additive or subtractive metallization procedures as is known in the art.
Using the Damascene Process, openings defining wiring patterns are provided in the dielectric layer, extending from one surface of the dielectric layer to the other surface of the dielectric layer. These wiring patterns are then filled with a metallization metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. This process may include planarization of the metal on the surface of the dielectric by removing excess metallization with a method such as chemical mechanical polishing (CMP).
In the single damascene process, vias or openings are additionally provided in the dielectric layer and filled with metallization to provide electrical contact between layers of wiring levels. In the dual damascene process, the via openings and the wiring pattern openings are both provided in the dielectric layer before filling with metallization. This process simplifies the procedure and eliminates some internal interfaces. These procedures are continued for each layer in the electronic component until the electronic component is completed.
In the formation of current laser metal fuse structures, one of the main problems that manufacturers encounter is the requirement of large spaces and a very complex processing operation, particularly involving copper. In addition, metal fuse rules are limited to particular restrictive values. Based on the foregoing, the present inventor has concluded that a need exists to reduce the space required in the formation of electrical metal fuses used in integrated circuit devices. The present inventor has also concluded that a need exists to reduce the processing complexity for copper based fabrication processes involved in the formal of electrical metal fuses. Finally, the present inventor recognizes that a need exists for methods and devices thereof that result in the generation of increased current density gradients and thermal gradients associated with electrical metal fuse structures. These needs and other goals can thus be met through the implementation of the methods and devices of the present invention disclosed herein.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present to provide an improved semiconductor manufacturing method and device thereof.
It is another aspect of the present invention to provide an improved method for forming an electrical metal fuse for use with semiconductor integrated circuit devices.
It is still another aspect of the present invention to provide a fuse structure having at least two different trench depths of copper to generate more current density gradients and thermal gradients thereof.
It is yet another aspect of the present invention to provide a fuse structure having at least two different widths of single copper lines to generate more current density gradients and thermal gradients thereof.
The above and other aspects of the present invention can thus be achieved as is now described. A method for forming an electrical metal fuse for use with a semiconductor integrated circuit device. At least two varying trench metal depths may be formed on a substrate to configure the electrical metal fuse thereon. Additionally, at least two different widths of single metal lines, may be configured on the substrate. As a result of the two different trench depths and two different widths of metal formed thereon to create the electrical metal fuse, increases in current density gradients and thermal gradients thereof can be generated. The trench metal depths and width of metal are formed from copper. The electrical metal fuse generally comprises a current density ratio greater than 10 to 1. The electrical metal fuse is generally formed as a result of an intermetal dielectric (IMD) deposition operation, followed by a via photolithography and etch operation. Thereafter, a metal photolithography and etch operation is performed to form a thinner layer. A metal photolithography and etch operation can additionally be performed to create a thinner layer upon the substrate. A copper plating operation can then be performed upon the substrate followed by a Chemical Mechanical Polishing (CMP) operation.